Halbleiterspeicher und Herstellungsverfahren

Mémoire à semi-conducteur et son procédé de fabrication

Semiconductor memory and method of manufacturing the same

Abstract

A method of producing a highly reliable mask ROM and the product produced by the method are disclosed. The method is characterized by comprising the steps of forming low doped source-drains to relax the electric field between the gate electrode and drain, thereby suppressing the creation of hot carriers, and of depositing dielectrics of a predetermined thickness between neighbouring gates to control the projection range of impurities implanted into the source-drain region of the bit into which data is to be written, the thickness of the dielectrics being determined such that the projection range does not exceed the junction depth of the source-drain in order to preclude the formation of parasitically doped layers which cause punch-through across an unwritten transistor.

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Patent Citations (3)

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    JP-S60241259-ANovember 30, 1985Hitachi Ltd, Hitachi Micro Comput Eng LtdManufacture of read only memory
    JP-S61218165-ASeptember 27, 1986Hitachi LtdSemiconductor memory and manufacture thereof
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NO-Patent Citations (2)

    Title
    PATENT ABSTRACTS OF JAPAN vol. 10, no. 99 (E-396)(2156) 16 April 1986 & JP-A-60 241 259 ( HITACHI MAIKURO COMPUTER ENGINEERING K.K. ) 30 November 1985
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    US-6562713-B1May 13, 2003International Business Machines CorporationMethod of protecting semiconductor areas while exposing a gate
    US-6642147-B2November 04, 2003International Business Machines CorporationMethod of making thermally stable planarizing films
    US-7316934-B2January 08, 2008Zavitan Semiconductors, Inc.Personalized hardware
    WO-0154194-A1July 26, 2001Zavitan Semiconductors, Inc.Personalized hardware